Submodel: MOSPD1
P-channel depletion MOSFET

Assumptions

This is a dynamic model of the p-channel depletion Metal Oxide Semiconductor Field Effect Transistor.

Symbol

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Interface

G gate
S source
D drain
B bulk

External Parameters

L = 100μ[m]channel length
W = 100μ[m]channel width
AS = 0[m2]source diffusion area
AD = 0[m2]drain diffusion area
PS = 0[m]source diffusion perimeter
PD = 0[m]drain diffusion perimeter
VTO = – 1[V]zero-bias threshold voltage (pos: enh./ neg: depl.)
KP = 2.105[A/V2]transconductance parameter
GAMMA = 0[V1/2]body-effect parameter
PHI = 0.6[V]surface inversion potential
LAMBDA = 0[1/V]channel-length modulation
TOX = 107[m]thin oxide thickness
NSUB = 0[cm3]substrate doping
NSS = 0[cm2]surface state density
LD = 0[m]lateral diffusion
TPG = + 1[–]type of gate material (+1 opp of sub/-1 same as sub/0 alu)
UO = 600[cm2/(Vs)]surface mobility
IS = 1014[A]bulk junction saturation current
JS = 0[A]bulk junction saturation current per square meter
PB = 0.8[V]bulk junction potential
CJ = 0[F/m2]zero-bias bulk capacitance per square meter
MJ = 0.5[–]bulk junction grading coefficient
CJSW = 0[F/m]zero-bias perimeter capacitance per meter
MJSW = 0.33[–]perimeter capacitance grading coefficient
FC = 0.5[–]forward-bias depletion capacitance coefficient
CGBO = 0[F/m]gate-bulk overlap capacitancee per meter
CGDO = 0[F/m]gate-drain overlap capacitancee per meter
CGSO = 0[F/m]gate-source overlap capacitancee per meter
RD = 0[Ω]drain ohmic resistance
RS = 0[Ω]source ohmic resistance
RSH = 0[Ω]source and drain sheet resistance
EG = 1.11[eV]bandgap voltage
GMIN = 1012[S]conductance to aid convergence

Description

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The metal-oxide-semiconductor field effect transistor model is derived from the model of Shichman and Hodges. The static current characteristic is defined by the parameters W, L, VT0, BETA, PHI, and GAMMA, which determine the variation of the drain current with gate, drain, and bulk voltages; LAMBDA, which determines the output conductance; and IS, the bulk junction saturation current. VTO is positive for the enhancement mode and negative for the depletion mode for N channel devices. Two ohmic resistances, RD and RS, are included. The two diodes model the source-substrate and drain-substrate junctions and are implemented by current-sources following the pn-junction equations. The charge-storage effect is represented by three nonlinear gate capacitors: CGB, CGS and CGD similar to the model proposed by Meyer. CGBO, CGSO and CGDO are the overlap capacitances among the gate electrode and the other terminals outside the channel region. The junction capacitances are calculated from the sum of an area and a perimeter capacitance using the parameters AS, AD, PS, PD, CJ, CJSW, MJ, MJSW, FC and PB.

Static model

The following equations are valid for [inline math] (normal mode). For VDS < 0 (inverted mode) the source and drain in the equations must be switched.

IDS [inline math] if VGS > VTH
Viq [inline math]  
VTH [inline math] threshold voltage
IBS [inline math]  
IBD [inline math]  
VBS = – (VBVSi) voltage across bulk-source junction
VBD = – (VBVDi) voltage across bulk-drain junction
VGS = – (VGVSi) voltage between gate and internal source node
VGD = – (VGVDi) voltage between gate and internal drain node
VDS = – (VDiVSi) voltage across the current source
Leff = L2LD effective length

The paramters VTO, KP, GAMMA, PHI, IS and PB are electrical parameters. If not specified directly, they can be calculated from geometrical, physical and technological parameters, using the following equations:

VTO [inline math]
KP [inline math]
GAMMA [inline math]
PHI [inline math]
IS [inline math]
PB [inline math]




Constants :

Vt [inline math] mV thermal voltage
εOX = kOXεO permittivity of the oxide
T = 300 K nominal temperature
q = 1.60 * 1019 As electron charge
k = 1.38 * 1023 J/K Boltzmann’s constant
εO = 8.85 * 1014 F/cm permittivity of free space
kOX = 3.9 dielectric constant of oxide (SiO2)
NI = 1.45 * 1010 cm3 intrinsic carrier concentration for Si

Dynamic model, similar to Meyer

COX [inline math]
VON = VTH



 Gate capacitance :
CGB [inline math]
CGS [inline math]
CGD [inline math]
 Junction capacitance :
F2 = (1FC)(1 + M)
F3 = 1FC(1 + M)
CBS [inline math]
CBD [inline math]

Data

:JW 16.02.00
:: P-channel depletion MOSFET
MOSPD1:: Dynamic model
G,  :: gate
S,  :: source
D,  :: drain
B/  :: bulk
L     = 100u,   ::[m] channel length
W     = 100u,   ::[m] channel width
AS    = 0,      ::[m^2] source diffusion area
AD    = 0,      ::[m^2] drain diffusion area
PS    = 0,      ::[m] source diffusion perimeter
PD    = 0,      ::[m] drain diffusion perimeter
VTO   = -1,     ::[V] zero-bias threshold voltage (pos: enh./ neg: depl.)
KP    = 2E-5,   ::[A/V^2] transconductance parameter
GAMMA = 0,      ::[V^{1/2}] body-effect parameter
PHI   = 0.6,    ::[V] surface inversion potential
LAMBDA= 0,      ::[1/V] channel-length modulation
TOX   = 1E-7,   ::[m] thin oxide thickness
NSUB  = 0,      ::[cm^-3] substrate doping
NSS   = 0,      ::[cm^-2] surface state density
LD    = 0,      ::[m] lateral diffusion
TPG   = +1,     ::[-] type of gate material (+1 opp of sub/-1 same as sub/0 alu)
UO    = 600,    ::[cm^2/(Vs)] surface mobility
IS    = 1E-14,  ::[A] bulk junction saturation current
JS    = 0,      ::[A] bulk junction saturation current per square meter
PB    = 0.8,    ::[V] bulk junction potential
CJ    = 0,      ::[F/m^2] zero-bias bulk capacitance per square meter
MJ    = 0.5,    ::[-] bulk junction grading coefficient
CJSW  = 0,      ::[F/m] zero-bias perimeter capacitance per meter
MJSW  = 0.33,   ::[-] perimeter capacitance grading coefficient
FC    = 0.5,    ::[-] forward-bias depletion capacitance coefficient
CGBO  = 0,      ::[F/m] gate-bulk overlap capacitancee per meter
CGDO  = 0,      ::[F/m] gate-drain overlap capacitancee per meter
CGSO  = 0,      ::[F/m] gate-source overlap capacitancee per meter
RD    = 0,      ::[Ohm] drain ohmic resistance
RS    = 0,      ::[Ohm] source ohmic resistance
RSH   = 0,      ::[Ohm] source and drain sheet resistance
EG    = 1.11,   ::[eV] bandgap voltage
GMIN = 1E-12;   ::[S] conductance to aid convergence
T  = 300;           :[K] nominal temperature
q  = 1.6021892E-19; :[As]  electron charge
k  = 1.380662E-23;  :[J/K] Boltzmann's constant
Vt = k*T/q;         :[V] thermal voltage
EO  = 8.85E-14;     :[F/cm] permittivity of free space
KOX = 3.9;          :[-] dielectric constant of oxide (SiO2)
EOX = KOX*EO;       :[F/cm] permittivity of the oxide
NI  = 1.45E+10;     :[cm^-3] intrinsic carrier concentration for Si
KS  = 11.8;         :[-] dielectric constant of material Si
ES  = KS*EO;        :[F/cm] permittivity of semiconductor
Leff= L - 2*LD;     :[m] effective length
ISD = IS*(JS=0 ! AD=0) + JS*AD;:(substrate-junction
ISS = IS*(JS=0 ! AS=0) + JS*AS;: saturation currents)
KPi = KP + (UO*EOX/TOX - 2E-5)*(KP=2E-5);
PHIi= PHI*(NSUB=0) + (2*Vt*LOG(NSUB/NI))*(NSUB>0);
GAMMAi= GAMMA + TOX/EOX*sqrt(2*q*ES*NSUB)*(GAMMA=0);
VTOi = (-TPG*EG/2 - PHI/2 - q*NSS*TOX/EOX + PHI
        + GAMMA*sqrt(PHI))*(TPG<1) + VTO*(TPG=1);
PBi  = PB*(NSUB=0) + (EG/2 + Vt*LOG(NSUB/NI))*(NSUB>0);
fd/exp/C=1/Vt,A=-1,L=0,SL=GMIN,U=10;:pn-junction function
VBS = -(V.B - V.Si); VBD = -(V.B - V.Di);
VGS = -(V.G - V.Si); VDS = -(V.Di - V.Si);
VGD = -(V.G - V.Di); VSD = -VDS;
VTH = VTO + GAMMAi*(sqrt(abs(PHIi-VBS))-sqrt(abs(PHIi)));
        :threshold voltage
VGSTH = VGS - VTH; VGDTH = VGD - VTH;
Viq = (VGSTH-VDS/2)*VDS*(VDS<VGSTH)     :linear forw.
            + .5*VGSTH**2*(VDS>VGSTH);  :saturated forw.
IDSx = KP*W/Leff*(1+LAMBDA*VDS)*Viq*(VGS>VTH);:forward
Viqr= (VGDTH-VSD/2)*VSD*(VSD<VGDTH)     :linear inv.
            + .5*VGDTH**2*(VSD>=VGDTH); :saturated inv.
ISDr= KP*W/Leff*(1+LAMBDA*VSD)*Viqr*(VGD>VTH);:inverse
IBSx = ISS*(fd(VBS)*(VBS>0) + (VBS/Vt)*(VBS<=0));
IBDx = ISD*(fd(VBD)*(VBD>0) + (VBD/Vt)*(VBD<=0));
:large signal model level 1 (similar to Meyer)
COX = EOX/TOX*Leff*W;
VON = VTH;
: gate capacitance, 4 regions:
reg = 1*(VGS<(VON-PHI))     :accumulation
    + 2*((VON-PHI)<VGS<VON) :depletion
    + 3*(VON<VGS<(VON+VDS)) :saturation
    + 4*(VGS>(VON+VDS));    :linear
zgs = 1 - ((VGS-VDS-VON)/(2*(VGS-VON)-VDS))**2;
zgd = 1 - ((VGS-VON)/(2*(VGS-VON)-VDS))**2;
CGB = CGBO*Leff + COX*(reg=1)
                + COX*(VON-VGS)/PHI*(reg=2);
CGS = CGSO*W + 2/3*COX*((VON-VGS)/PHI + 1)*(reg=2)
             + 2/3*COX*(reg=3)
             + COX*zgs*(reg=4);
CGD = CGDO*W + COX*zgd*(reg=4);
: junction capacitance
F2 = (1-FC)**(1+MJ);
F3 = 1 - FC*(1+MJ);
CBS1= CJ*AS/(abs(1-VBS/PBi)**MJ)
        + CJSW*PS/(abs(1-VBS/PBi)**MJSW);
CBS2= F3/F2*(CJ*AS+CJSW*PS)
        + VBS/(PBi*F2)*(CJ*AS*MJ+CJSW*PS*MJSW);
CBS = CBS1*(VBS<(FC*PBi)) + CBS2*(VBS>=(FC*PBi));
CBD1= CJ*AD/(abs(1-VBD/PBi)**MJ)
        + CJSW*PD/(abs(1-VBD/PBi)**MJSW);
CBD2= F3/F2*(CJ*AD+CJSW*PD)
        + VBD/(PBi*F2)*(CJ*AD*MJ+CJSW*PD*MJSW);
CBD = CBD1*(VBD<(FC*PBi)) + CBD2*(VBD>=(FC*PBi));
:substitute circuit
Cgbi G-B  = CGB;
Cgsi G-Si = CGS;
Cgdi G-Di = CGD;
Cbsi B-Si = CBS;
Cbdi B-Di = CBD;
IDS > J Di-Si = -IDSx*(VDS>=0) + ISDr*(VDS<0);:current source
IBS > J B-Si  = -IBSx;:B-S diode
IBD > J B-Di  = -IBDx;:B-D diode
Rsi Si-S  = RS;
Rdi Di-D  = RD;
EO@;

Origin

This model is similar to the LEVEL 1 model of the MOSFET implemented in SPICE2.
Wolff J.

 [1] Massobrio G., Antognetti P. Semiconductor Device Modeling With SPICE. Second Edition, McGraw-Hill Inc. 1993, p.131-148.

Last Update

May 12, 2005